1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to dynamic logic circuits.
2. Description of the Related Art
Dynamic logic circuits are well known in the electronic arts. Operation of a dynamic circuit may be divided into a precharge phase and an evaluate phase. During the precharge phase, a dynamic node may be precharged to a logic high voltage. The precharge may be accomplished by a PMOS (p-channel metal oxide semiconductor) transistor coupled between the dynamic node and a voltage supply node. During the evaluation phase, the dynamic node may either be discharged low or may be held high, depending on the input to the dynamic circuit. For example, if an NMOS (n-channel metal oxide semiconductor) transistor is coupled between the dynamic node and a ground node, the dynamic node may be pulled low during the evaluation phase if the input (i.e. the gate terminal of the NMOS transistor) is high, thus activating the NMOS device. Otherwise, if the NMOS device remains inactive during the evaluation phase (i.e. the gate terminal is low), the dynamic node may be held high. A keeper or half-keeper device may be included in the dynamic logic circuit to hold the dynamic node high if it evaluates high during the evaluation phase.
The precharge and evaluation phases in many dynamic logic circuits may be controlled by a clock signal. The precharge phase may occur during the low phase of the clock cycle, while the evaluation phase may occur during the high phase of the clock cycle. The clock signal may be provided to the gate terminal of a PMOS transistor coupled between the dynamic node and the voltage supply node. Thus, when the gate terminal is low (due to the clock low), the PMOS transistor will turn on and precharge the dynamic node. When the clock transitions high, the PMOS transistor will turn off, thus enabling the evaluation phase to begin.